VHDL PROGRAM FOR SERIAL IN SERIAL OUT SHIFT REGISTER IN BEHAVIOURAL STYLE

library ieee;
use ieee.std_logic_1164.all;
entity shiftsi is
port(C, SI : in std_logic;
SO : out std_logic);
end shiftsi;
architecture archi of shiftsi is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
tmp(0) <= SI;
if (C'event and C='1') then
for i in 0 to 6 loop
tmp(i+1) <= tmp(i);
end loop;

end if;
end process;
SO <= tmp(7);
end archi;