VHDL PROGRAM FOR DECADE COUNTER IN STRUCTURAL STYLE-IC 7490

library ieee;
use ieee.std_logic_1164.all;
entity ic7490 is
port(ms1,ms2,mr1,mr2,clk:in bit;
q:inout bit_vector(3 downto 0));
end ic7490;
architecture ic7490_arch of ic7490 is
component nandgate
port(a,b:in bit; c:out bit);
end component;
component andgate
port(a,b:in bit; c:out bit);
end component;

component jkff
port(j,k,clk,sd_l,rd_l:in bit;
q,q_l:inout bit);
end component;
signal ms,mr,a2:bit;
signal q_l:bit_vector(3 downto 0);
signal j,k:bit:='1';

begin
L1:nandgate port map(ms1,ms2,ms);
L2:nandgate port map(mr1,mr2,mr);
L3:andgate port map(q(1),q(2),a2);
L6:jkff port map(j,k,clk,ms,mr,q(0),q_l(0));
L7:jkff port map(q_l(3),k,q(0),ms,mr,q(1),q_l(1));
L8:jkff port map(j,k,q(1),ms,mr,q(2),q_l(2));
L9:jkff port map(a2,k,q(0),ms,mr,q(3),q_l(3));
end ic7490_arch;

0 comments: