VHDL PROGRAM FOR RS FLIPFLOP IN STRUCTURAL STYLE

library ieee;
use ieee.std_logic_1164.all;
entity rsff is
port(r,s,clk,sd_l,rd_l:in bit;
q,q_l:inout bit);
end rsff;
architecture rsff_arch of rsff is
begin
process(clk)
begin
if(rd_l='0' and sd_l='1')
then q<='0';
elsif(rd_l='1' and sd_l='0')
then q<='1';
elsif(rd_l='1' and sd_l='1')
then
if(clk'event and clk='0') then
if(r='0' and s='1') then q<='1';
elsif(r='1' and s='0') then q<='0';
elsif(r='0' and s='0') then q<=q;
end if;
end if;
end if;

end process;
q_l<= not q;

end rsff_arch;