VHDL FROGRAM FOR jk-flipflop in BEHAVIOURAL STYLE

library ieee;
use ieee.std_logic_1164.all;
entity jkff is
port(j,k,clk,sd_l,rd_l:in bit;
q,q_l:inout bit);
end jkff;

architecture jkff_arch of jkff is
begin
process(clk)
begin
if(rd_l='0' and sd_l='1')
then q<='0';
elsif(rd_l='1' and sd_l='0')
then q<='1';
elsif(rd_l='1' and sd_l='1')
then if(clk'event and clk='0')
then
if(j='0' and k='1') then q<='0';
elsif(j='1' and k='0') then q<='1';
elsif(j='0' and k='0') then q<=q;
elsif(j='1' and k='1') then q<=not q;
end if;
end if;
end if;
end process;
q_l<=not q;
end jkff_arch;