VHDL PROGRAM FOR D-flipflop in STRUCTURAL STYLE-IC7474

library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(pre_l,clr_l,d,clk:in std_logic;
q,q_l:inout std_logic);
end dff;
architecture dff_arch of dff is
signal qa,qb,qc,qd:std_logic;
component nand3d
port(a,b,c:in std_logic; y:inout std_logic);
end component;
begin
L1:nand3d port map(pre_l,qd,qb,qa);
L2:nand3d port map(clr_l,qa,clk,qb);
L3:nand3d port map(clk,qb,qd,qc);
L4:nand3d port map(d,clr_l,qc,qd);
L5:nand3d port map(pre_l,qb,q_l,q);
L6:nand3d port map(clr_l,qc,q,q_l);
end dff_arch;