VHDL PROGRAM FOR 4-bit BIDIRECTIONAL UNIVERSAL SHIFT REGISTER IN STRUCTURAL STYLE-IC 74LS194

library ieee;
use ieee.std_logic_1164.all;
entity universal is
port(clk,clr_l,Lin,Rin,s1,s0:in std_logic;
a,b,c,d:in std_logic;
q:inout std_logic_vector(3 downto 0));
end universal;
architecture universal of universal is
component and3
port(a,b,c:in std_logic;y:out std_logic);
end component;

component or4
port(a,b,c,d:in std_logic;y:out std_logic);
end component;

component not1
port(a:in std_logic;b:out std_logic);
end component;

component dff
port(pre_l,clr_l,d,clk:in std_logic;q,q_l:inout std_logic);
end component;

signal s1_l,s0_l:std_logic;
signal q_l:std_logic_vector(3 downto 0);
signal s:std_logic_vector(1 to 20);
signal pr:std_logic;
begin
l1:not1 port map(s1,s1_l);
l2:not1 port map(s0,s0_l);
l3:and3 port map(Lin,s1,s0_l,s(1));
l4:and3 port map(q(0),s1_l,s0_l,s(2));
l5:and3 port map(d,s1,s0,s(3));
l6:and3 port map(q(1),s1_l,s0,s(4));
l7:or4 port map(s(1),s(2),s(3),s(4),s(5));
--18:not1 port map(clr_l,clr);
l9:dff port map(pr,clr_l,s(5),clk,q(0),q_l(0));
l10:and3 port map(q(0),s1,s0_l,s(6));
l11:and3 port map(q(1),s1_l,s0_l,s(7));
l12:and3 port map(c,s1,s0,s(8));
l13:and3 port map(q(2),s1_l,s0,s(9));
l14:or4 port map(s(6),s(7),s(8),s(9),s(10));
l15:dff port map(pr,clr_l,s(10),clk,q(1),q_l(1));
l16:and3 port map(q(1),s1,s0_l,s(11));
l17:and3 port map(q(2),s1_l,s0_l,s(12));
l18:and3 port map(b,s1,s0,s(13));
l19:and3 port map(q(3),s1_l,s0,s(14));
l20:or4 port map(s(11),s(12),s(13),s(14),s(15));
l21:dff port map(pr,clr_l,s(15),clk,q(2),q_l(2));
l22:and3 port map(q(2),s1,s0_l,s(16));
l23:and3 port map(q(3),s1_l,s0_l,s(17));
l24:and3 port map(a,s1,s0,s(18));
l25:and3 port map(Rin,s1_l,s0,s(19));
l26:or4 port map(s(16),s(17),s(18),s(19),s(20));
l27:dff port map(pr,clr_l,s(20),clk,q(3),q_l(3));
end universal;