wideband wireless antenna ieee paper

IEEE paper on wireless antenna.......

http://www.ziddu.com/download/6852600/ieeepaperwidebandwirelessantenna.pdf.html


useful for engineering students in ece stream and for those who are interested in antennas

vlsi advancements

Advancements in VLSI has made it attractive to package multiple processors into a single multichip
or a board module. There is an increasing trend towards using such processor-clusters in
large multiprocessor design. Past research on designing processor-cluster based systems has focused
mainly in studying the packaging technologies affecting the inter-cluster network. To make
processor-cluster based multiprocessor design more attractive, there is a strong need to understand
the details about the topology inside the cluster, its memory organization, and the impact of this
organization on system performance. In this paper we focus on such aspects of processor-cluster
design with an overall objective to support a logically shared address programming model. We analyze
the communication costs for accesing inter-cluster and intra-cluster memories under different
cluster organizations. The merits of these organizations are evaluated based on the performance
of collective communication algorithms, which occur frequently in appplications. In this paper
we focus on implementing the broadcast collective communication algorithm, Umesh, on clustered
systems. Our results indicate that cluster organizations like bus and crossbar which allow memory
inside a cluster to be accessed without messaging overheads, outperform other organizations because
of faster intra-cluster access. We also demonstrate that such faster access can be exploited to
design better algorithms on clustered systems. We propose a new algorithm - clus mesh for broadcasting
on clustered meshes. For reasonably faster communication within clusters, this algorithm
can outperform the existing umesh algorithm by upto 20%.

VHDL PROGRAM FOR GENERATING A CLOCK WITH a period of 40ns

hi FRIENDS,
A simple program to generate a clock in VHDL PROGRAMMING.
wait statement is used for delaying.


library ieee;

use ieee.std_logic_1164.all;

entity clkgen is
end clkgen;
architecture clk of clkgen is
constant num_cycles:integer:=10;
signal clk:std_logic:='1';
begin
process
begin
for i in 1 to num_cycles loop
wait for 20 ns;
clk<= not clk;
wait for 20 ns;
end loop;

end process;
end clk;

VHDL PROGRAM FOR THREE INPUT LOGIC GATES USING CASE STATEMENT IN BEHAVIOURAL STYLE

library IEEE;
use IEEE.std_logic_1164.all;
entity comp is
port (
altbin: in STD_LOGIC;
aeqbin: in STD_LOGIC;
agtbin: in STD_LOGIC;
a: in STD_LOGIC_VECTOR (3 downto 0);
b: in STD_LOGIC_VECTOR (3 downto 0);
agtbout: out STD_LOGIC;
aeqbout: out STD_LOGIC;
altbout: out STD_LOGIC
);
end comp;
architecture comp of comp is
begin
process(a,b,agtbin,aeqbin,altbin)
begin
agtbout<='0'; --initializes the outputs to ‘0’
aeqbout<='0';
altbout<='0';
if aeqbin='1' then
if a=b then aeqbout<='1';
elsif a>b then agtbout<='1';
elsif (a
end if;
elsif (altbin/=agtbin)then
agtbout<=agtbin;
altbout<=altbin;
end if;
end process;
end Comp;

VHDL PROGRAM FOR COMPARATOR IN BEHAVIOURAL STYLE

library IEEE;
use IEEE.std_logic_1164.all;
entity comp is
port (
altbin: in STD_LOGIC;
aeqbin: in STD_LOGIC;
agtbin: in STD_LOGIC;
a: in STD_LOGIC_VECTOR (3 downto 0);
b: in STD_LOGIC_VECTOR (3 downto 0);
agtbout: out STD_LOGIC;
aeqbout: out STD_LOGIC;
altbout: out STD_LOGIC
);
end comp;
architecture comp of comp is
begin
process(a,b,agtbin,aeqbin,altbin)
begin
agtbout<='0'; --initializes the outputs to ‘0’
aeqbout<='0';
altbout<='0';
if aeqbin='1' then
if a=b then aeqbout<='1';
elsif a>b then agtbout<='1';
elsif (a
end if;
elsif (altbin/=agtbin)then
agtbout<=agtbin;
altbout<=altbin;
end if;
end process;
end Comp;

VHDL PROGRAM FOR SERIAL IN SERIAL OUT SHIFT REGISTER IN BEHAVIOURAL STYLE

library ieee;
use ieee.std_logic_1164.all;
entity shiftsi is
port(C, SI : in std_logic;
SO : out std_logic);
end shiftsi;
architecture archi of shiftsi is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
tmp(0) <= SI;
if (C'event and C='1') then
for i in 0 to 6 loop
tmp(i+1) <= tmp(i);
end loop;

end if;
end process;
SO <= tmp(7);
end archi;

VHDL PROGRAM FOR 4X2 ENCODER IN DATAFLOW STYLE

library ieee;
use ieee.std_logic_1164.all;
entity encod4to2 is
port(d:in std_logic_vector(3 downto 0);
a:out std_logic_vector(1 downto 0));
end encod4to2;
architecture encod4to2 of encod4to2 is
begin
a(0)<=d(1) or d(3);
a(1)<=d(2) or d(3);
end encod4to2;

VHDL PROGRAM FOR 4-bit BINARY ADDER SUBTRACTOR IN STRUCTURAL STYLE

library ieee;
use ieee.std_logic_1164.all;
entity bin4bitaddsub is
port(a,b:in std_logic_vector(3 downto 0);
s:out std_logic_vector(3 downto 0);
cin: in std_logic;
cout:out std_logic);
end bin4bitaddsub;
architecture bin4bitaddsub of bin4bitaddsub is
signal c:std_logic_vector(0 to 2);
signal d:std_logic_vector(3 downto 0);
component xor_2
port(a,b:in std_logic;
c:out std_logic);
end component;
component fulladdD
port(x,y,cin:in std_logic;
s,cout:out std_logic);
end component;
begin
l1:xor_2 port map(b(0),cin,d(0));
l2:xor_2 port map(b(1),cin,d(1));
l3:xor_2 port map(b(2),cin,d(2));
l4:xor_2 port map(b(3),cin,d(3));
l5:fulladdD port map(a(0),d(0),cin,s(0),c(0));
l6:fulladdD port map(a(1),d(1),c(0),s(1),c(1));
l7:fulladdD port map(a(2),d(2),c(1),s(2),c(2));
l8:fulladdD port map(a(3),d(3),c(2),s(3),cout);
end bin4bitaddsub;

library ieee;
use ieee.std_logic_1164.all;
entity xor_2 is
port(a,b:in std_logic;
c:out std_logic);
end xor_2;
architecture xor2 of xor_2 is
begin
c<=a xor b;
end xor2;

library ieee;
use ieee.std_logic_1164.all;
entity fulladdD is
port(x,y,cin:in std_logic;
s,cout:out std_logic);
end fulladdD;
architecture full of fulladdD is
begin
s <= x xor y xor cin;
cout<=(x and y) or (x and cin) or (y and cin);
end full;

VHDL PROGRAM FOR D-flipflop in STRUCTURAL STYLE-IC7474

library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(pre_l,clr_l,d,clk:in std_logic;
q,q_l:inout std_logic);
end dff;
architecture dff_arch of dff is
signal qa,qb,qc,qd:std_logic;
component nand3d
port(a,b,c:in std_logic; y:inout std_logic);
end component;
begin
L1:nand3d port map(pre_l,qd,qb,qa);
L2:nand3d port map(clr_l,qa,clk,qb);
L3:nand3d port map(clk,qb,qd,qc);
L4:nand3d port map(d,clr_l,qc,qd);
L5:nand3d port map(pre_l,qb,q_l,q);
L6:nand3d port map(clr_l,qc,q,q_l);
end dff_arch;

VHDL PROGRAM FOR 4-bit BINARY COUNTER IN STRUCTURAL STYLE-IC 7493

library ieee;
use ieee.std_logic_1164.all;
entity ic7493 is
port(clk,mr1,mr2,sd_l:in bit;
q:inout bit_vector(3 downto 0));
end ic7493;

architecture ic7493_arch of ic7493 is
component notgate
port(a:in bit; b:out bit);
end component;

component nandgate
port(a,b:in bit; c:out bit);
end component;
component jkff
port(j,k,clk,sd_l,rd_l:in bit;
q:inout bit);
end component;
signal j1,k1:bit:='1';
signal mr_l:bit;

begin
L1:nandgate port map(mr1,mr2,mr_l);

L5:jkff port map(j1,k1,clk,sd_l,mr_l,q(0));
L6:jkff port map(j1,k1,q(0),sd_l,mr_l,q(1));
L7:jkff port map(j1,k1,q(1),sd_l,mr_l,q(2));
l8:jkff port map(j1,k1,q(2),sd_l,mr_l,q(3));
end ic7493_arch;

VHDL PROGRAM FOR DECADE COUNTER IN STRUCTURAL STYLE-IC 7490

library ieee;
use ieee.std_logic_1164.all;
entity ic7490 is
port(ms1,ms2,mr1,mr2,clk:in bit;
q:inout bit_vector(3 downto 0));
end ic7490;
architecture ic7490_arch of ic7490 is
component nandgate
port(a,b:in bit; c:out bit);
end component;
component andgate
port(a,b:in bit; c:out bit);
end component;

component jkff
port(j,k,clk,sd_l,rd_l:in bit;
q,q_l:inout bit);
end component;
signal ms,mr,a2:bit;
signal q_l:bit_vector(3 downto 0);
signal j,k:bit:='1';

begin
L1:nandgate port map(ms1,ms2,ms);
L2:nandgate port map(mr1,mr2,mr);
L3:andgate port map(q(1),q(2),a2);
L6:jkff port map(j,k,clk,ms,mr,q(0),q_l(0));
L7:jkff port map(q_l(3),k,q(0),ms,mr,q(1),q_l(1));
L8:jkff port map(j,k,q(1),ms,mr,q(2),q_l(2));
L9:jkff port map(a2,k,q(0),ms,mr,q(3),q_l(3));
end ic7490_arch;

VHDL PROGRAM FOR 4-bit SHIFT REGISTER IN STRUCTURAL STYLE-IC 74LS94

library ieee;
use ieee.std_logic_1164.all;
entity shiftreg is
port(mode,sin,rsh,lsh:in bit;
qin:in bit_vector(0 to 3);
qout:inout bit_vector(0 to 3));
end shiftreg;
architecture shiftreg_arch of shiftreg is
signal mode_l,clk:bit;
signal sd_l,rd_l:bit:='1';
signal p:bit_vector(0 to 9);
signal t,t_l,qout_l:bit_vector(0 to 3);
component notgate
port(a:in bit; b:out bit);
end component;
component andgate
port(a,b:in bit;c:out bit);
end component;
component norgate
port(a,b:in bit;c:out bit);
end component;
component orgate
port(a,b:in bit; c:out bit);
end component;
component rsff
port(r,s,clk,sd_l,rd_l:in bit;
q,q_l:inout bit);
end component;
begin
L1:notgate port map(mode,mode_l);
L2:andgate port map(sin,mode_l,p(0));
L3:andgate port map(mode,qin(0),p(1));
L4:andgate port map(mode_l,qout(0),p(2));
L5:andgate port map(mode,qin(1),p(3));
L6:andgate port map(mode,qout(1),p(4));
L7:andgate port map(mode,qin(2),p(5));
L8:andgate port map(mode_l,qout(2),p(6));
L9:andgate port map(mode,qin(3),p(7));
L10:andgate port map(mode_l,rsh,p(8));
L11:andgate port map(mode,lsh,p(9));
L12:norgate port map(p(0),p(1),t(0));
L13:norgate port map(p(2),p(3),t(1));
L14:norgate port map(p(4),p(5),t(2));
L15:norgate port map(p(6),p(7),t(3));
L16:orgate port map(p(8),p(9),clk);
L17:notgate port map(t(0),t_l(0));
L18:notgate port map(t(1),t_l(1));
L19:notgate port map(t(2),t_l(2));
L20:notgate port map(t(3),t_l(3));
L21:rsff port map(t(0),t_l(0),clk,sd_l,rd_l,qout(0),qout_l(0));
L22:rsff port map(t(1),t_l(1),clk,sd_l,rd_l,qout(1),qout_l(1));
L23:rsff port map(t(2),t_l(2),clk,sd_l,rd_l,qout(2),qout_l(2));
L24:rsff port map(t(3),t_l(3),clk,sd_l,rd_l,qout(3),qout_l(3));
end shiftreg_arch;

VHDL FROGRAM FOR jk-flipflop in BEHAVIOURAL STYLE

library ieee;
use ieee.std_logic_1164.all;
entity jkff is
port(j,k,clk,sd_l,rd_l:in bit;
q,q_l:inout bit);
end jkff;

architecture jkff_arch of jkff is
begin
process(clk)
begin
if(rd_l='0' and sd_l='1')
then q<='0';
elsif(rd_l='1' and sd_l='0')
then q<='1';
elsif(rd_l='1' and sd_l='1')
then if(clk'event and clk='0')
then
if(j='0' and k='1') then q<='0';
elsif(j='1' and k='0') then q<='1';
elsif(j='0' and k='0') then q<=q;
elsif(j='1' and k='1') then q<=not q;
end if;
end if;
end if;
end process;
q_l<=not q;
end jkff_arch;

VHDL PROGRAM FOR 4-bit BIDIRECTIONAL UNIVERSAL SHIFT REGISTER IN STRUCTURAL STYLE-IC 74LS194

library ieee;
use ieee.std_logic_1164.all;
entity universal is
port(clk,clr_l,Lin,Rin,s1,s0:in std_logic;
a,b,c,d:in std_logic;
q:inout std_logic_vector(3 downto 0));
end universal;
architecture universal of universal is
component and3
port(a,b,c:in std_logic;y:out std_logic);
end component;

component or4
port(a,b,c,d:in std_logic;y:out std_logic);
end component;

component not1
port(a:in std_logic;b:out std_logic);
end component;

component dff
port(pre_l,clr_l,d,clk:in std_logic;q,q_l:inout std_logic);
end component;

signal s1_l,s0_l:std_logic;
signal q_l:std_logic_vector(3 downto 0);
signal s:std_logic_vector(1 to 20);
signal pr:std_logic;
begin
l1:not1 port map(s1,s1_l);
l2:not1 port map(s0,s0_l);
l3:and3 port map(Lin,s1,s0_l,s(1));
l4:and3 port map(q(0),s1_l,s0_l,s(2));
l5:and3 port map(d,s1,s0,s(3));
l6:and3 port map(q(1),s1_l,s0,s(4));
l7:or4 port map(s(1),s(2),s(3),s(4),s(5));
--18:not1 port map(clr_l,clr);
l9:dff port map(pr,clr_l,s(5),clk,q(0),q_l(0));
l10:and3 port map(q(0),s1,s0_l,s(6));
l11:and3 port map(q(1),s1_l,s0_l,s(7));
l12:and3 port map(c,s1,s0,s(8));
l13:and3 port map(q(2),s1_l,s0,s(9));
l14:or4 port map(s(6),s(7),s(8),s(9),s(10));
l15:dff port map(pr,clr_l,s(10),clk,q(1),q_l(1));
l16:and3 port map(q(1),s1,s0_l,s(11));
l17:and3 port map(q(2),s1_l,s0_l,s(12));
l18:and3 port map(b,s1,s0,s(13));
l19:and3 port map(q(3),s1_l,s0,s(14));
l20:or4 port map(s(11),s(12),s(13),s(14),s(15));
l21:dff port map(pr,clr_l,s(15),clk,q(2),q_l(2));
l22:and3 port map(q(2),s1,s0_l,s(16));
l23:and3 port map(q(3),s1_l,s0_l,s(17));
l24:and3 port map(a,s1,s0,s(18));
l25:and3 port map(Rin,s1_l,s0,s(19));
l26:or4 port map(s(16),s(17),s(18),s(19),s(20));
l27:dff port map(pr,clr_l,s(20),clk,q(3),q_l(3));
end universal;

VHDL PROGRAM FOR T-FLIPFLOP IN BEHAVIOURAL STYLE

library ieee;
use ieee.std_logic_1164.all;
entity tff1 is
port(t,sd_l,rd_l,clk:in bit; q:inout bit);
end tff1;
architecture tff1_arch of tff1 is
begin
process(clk)
begin

if(sd_l='1' and rd_l='0') then
q<='0';
elsif(sd_l='0' and rd_l='1') then
q<='1';
elsif(sd_l='1' and rd_l='1') then
if(clk'event and clk='0') then
if(t='0') then q<='0';
elsif(t='1') then q<=not q;
end if;
end if;
end if;

end process;


end tff1_arch;

VHDL PROGRAM FOR RS FLIPFLOP IN STRUCTURAL STYLE

library ieee;
use ieee.std_logic_1164.all;
entity rsff is
port(r,s,clk,sd_l,rd_l:in bit;
q,q_l:inout bit);
end rsff;
architecture rsff_arch of rsff is
begin
process(clk)
begin
if(rd_l='0' and sd_l='1')
then q<='0';
elsif(rd_l='1' and sd_l='0')
then q<='1';
elsif(rd_l='1' and sd_l='1')
then
if(clk'event and clk='0') then
if(r='0' and s='1') then q<='1';
elsif(r='1' and s='0') then q<='0';
elsif(r='0' and s='0') then q<=q;
end if;
end if;
end if;

end process;
q_l<= not q;

end rsff_arch;

VHDL PROGRAM FOR PRIME NUMBERS IN STRUCTURAL STYLE

library ieee;
use ieee.std_logic_1164.all;
entity or4 is
port(i0,i1,i2,i3:in std_logic;o:out std_logic);
end or4;
architecture or2 of or4 is
begin
o<=i0 or i1 or i2 or i3;
end or2;


library ieee;
use ieee.std_logic_1164.all;
entity and2 is
port(i0,i1:in std_logic;o:out std_logic);
end and2;
architecture and2_arch of and2 is
begin
o<=i0 and i1;
end and2_arch;


library ieee;
use ieee.std_logic_1164.all;
entity and3 is
port(i0,i1,i2:in std_logic;o:out std_logic);
end and3;
architecture and3_arch of and3 is
begin
o<=i0 and i1 and i2;
end and3_arch;


library ieee;
use ieee.std_logic_1164.all;
entity inv is
port(i:in std_logic; o:out std_logic);
end inv;
architecture inv_arch of inv is
begin
o<=not i ;
end inv_arch;

library ieee;
use ieee.std_logic_1164.all;
entity prime is
port(n: in std_logic_vector(3 downto 0);
f:out std_logic);
end prime;

architecture prime1_arch of prime is
signal x1,x2,x3,a1,a2,a3,a4 :std_logic;
component INV port(i:in std_logic; o:out std_logic); end component;
component and2 port(i0,i1:in std_logic; o:out std_logic); end component;
component and3 port(i0,i1,i2:in std_logic; o:out std_logic); end component;
component or4 port(i0,i1,i2,i3:in std_logic; o:out std_logic); end component;
begin
U1:INV port map(n(3),x1);
U2:INV port map(n(2),x2);
U3:INV port map(n(1),x3);
U4:AND2 port map(x1,n(0),a1);
U5:AND3 PORT MAP(x1,x2,n(1),a2);
U6:AND3 port map(x2,n(1),n(0),a3);
U7:AND3 port map(n(2),x3,n(0),a4);
U8:or4 port map(a1,a2,a3,a4,f);
end prime1_arch;

PROGRAM FOR 3X8 DECODER IN STRUCTURAL STYLE

library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port(g1,g2a_l,g2b_l:in std_logic;
a,b,c:in std_logic;
d_l:out std_logic_vector(7 downto 0));
end decoder;

architecture dec of decoder is
signal g2a,g2b,en:std_logic;
signal a_l,b_l,c_l:std_logic;

component not1
port(a:in std_logic;b:out std_logic);
end component;

component and3
port(a0,a1,a2:in std_logic;y3:out std_logic);
end component;

component nand4
port(a0,a1,a2,a3:in std_logic;y4:out std_logic);
end component;

begin
L1:not1 port map(g2a_l,g2a);
L2:not1 port map(g2b_l,g2b);
L3:not1 port map(a,a_l);
L4:not1 port map(b,b_l);
L5:not1 port map(c,c_l);
L :and3 port map(g1,g2a,g2b,en);

L6:nand4 port map(en,a_l,b_l,c_l,d_l(0));
L7:nand4 port map(en,a_l,b_l,c,d_l(1));
L8:nand4 port map(en,a_l,b,c_l,d_l(2));
L9:nand4 port map(en,a_l,b,c,d_l(3));
L10:nand4 port map(en,a,b_l,c_l,d_l(4));
L11:nand4 port map(en,a,b_l,c,d_l(5));
L12:nand4 port map(en,a,b,c_l,d_l(6));
L13:nand4 port map (en,a,b,c,d_l(7));
end dec;


library ieee; --program for not gate
use ieee.std_logic_1164.all;
entity not1 is
port(a:in std_logic;b:out std_logic);
end not1;
architecture not2 of not1 is
begin
b<=not a;
end not2;

library ieee; ----program for 3 input and gate
use ieee.std_logic_1164.all;
entity and3 is
port(a0,a1,a2:in std_logic;y3:out std_logic);
end and3;
architecture and1 of and3 is
begin
y3<=a0 and a1 and a2;
end and1;

library ieee; ----program for 4 input nand gate
use ieee.std_logic_1164.all;
entity nand4 is
port(a0,a1,a2,a3:in std_logic;y4:out std_logic);
end nand4;
architecture nand3 of nand4 is
signal y4_l:std_logic;
begin
y4_l<=a0 and a1 and a2 and a3;
y4<=not y4_l;
end nand3;

VHDL PROGRAM for COMPARATOR in STRUCTURAL style

FRIENDS,
you need to write the program for the components that were declared in order to compile this and run this program.



library ieee;
use ieee.std_logic_1164.all;
entity comp4 is
port(aeqbin,agtbin,altbin:in std_logic;
a,b:in std_logic_vector(3 downto 0);
aeqbout,agtbout,altbout:out std_logic);
end comp4;
architecture comp4_arch of comp4 is
component and2
port(a,b:in std_logic;y:out std_logic);
end component;

component and3
port(a,b,c:in std_logic;y:out std_logic);
end component;

component and4
port(a,b,c,d:in std_logic;y:out std_logic);
end component;

component and5
port(a,b,c,d,e:in std_logic;y:out std_logic);
end component;
component nand2
port(a,b:in std_logic; y:out std_logic);
end component;

component nor2
port(a,b:in std_logic;y:out std_logic);
end component;
component nor6
port(a,b,c,d,e,f:in std_logic; y:out std_logic);
end component;
signal s,p:std_logic_vector(3 downto 0);
signal r:std_logic_vector(7 downto 0);
signal q:std_logic_vector(11 downto 0);
begin
L1:nand2 port map(a(0),b(0),s(0));
L2:nand2 port map(a(1),b(1),s(1));
L3:nand2 port map(a(2),b(2),s(2));
L4:nand2 port map(a(3),b(3),s(3));
L5:and2 port map(s(3),a(3),r(0));
L6:and2 port map(s(3),b(3),r(1));
L7:and2 port map(s(2),a(2),r(2));
L8:and2 port map(s(2),b(2),r(3));
L9:and2 port map(s(1),a(1),r(4));
L10:and2 port map(s(1),b(1),r(5));
L11:and2 port map(s(0),a(0),r(6));
L12:and2 port map(s(0),b(0),r(7));
L13:nor2 port map(r(0),r(1),p(0));
L14:nor2 port map(r(2),r(3),p(1));
L15:nor2 port map(r(4),r(5),p(2));
L16:nor2 port map(r(6),r(7),p(3));
L17:and2 port map(s(3),b(3),q(0));
L18:and3 port map(p(0),s(2),b(2),q(1));
L19:and4 port map(b(1),s(1),p(0),p(1),q(2));
L20:and5 port map(b(0),s(0),p(0),p(1),p(2),q(3));
L21:and5 port map(p(0),p(1),p(2),p(3),altbin,q(4));
L22:and5 port map(p(0),p(1),p(2),p(3),aeqbin,q(5));
L23:and5 port map(p(0),p(1),p(2),p(3),aeqbin,q(6));
L24:and5 port map(p(0),p(1),p(2),p(3),agtbin,q(7));
L25:and5 port map(a(0),s(0),p(0),p(1),p(2),q(8));
L26:and4 port map(a(1),s(1),p(0),p(1),q(9));
L27:and3 port map(a(2),s(2),p(0),q(10));
L28:and2 port map(a(3),s(3),q(11));
L29:and5 port map(p(0),p(1),p(2),p(3),aeqbin,aeqbout);
L30:nor6 port map(q(0),q(1),q(2),q(3),q(4),q(5),agtbout);
L31:nor6 port map(q(6),q(7),q(8),q(9),q(10),q(11),altbout);
end comp4_arch;