PROGRAM FOR 3X8 DECODER IN STRUCTURAL STYLE

library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port(g1,g2a_l,g2b_l:in std_logic;
a,b,c:in std_logic;
d_l:out std_logic_vector(7 downto 0));
end decoder;

architecture dec of decoder is
signal g2a,g2b,en:std_logic;
signal a_l,b_l,c_l:std_logic;

component not1
port(a:in std_logic;b:out std_logic);
end component;

component and3
port(a0,a1,a2:in std_logic;y3:out std_logic);
end component;

component nand4
port(a0,a1,a2,a3:in std_logic;y4:out std_logic);
end component;

begin
L1:not1 port map(g2a_l,g2a);
L2:not1 port map(g2b_l,g2b);
L3:not1 port map(a,a_l);
L4:not1 port map(b,b_l);
L5:not1 port map(c,c_l);
L :and3 port map(g1,g2a,g2b,en);

L6:nand4 port map(en,a_l,b_l,c_l,d_l(0));
L7:nand4 port map(en,a_l,b_l,c,d_l(1));
L8:nand4 port map(en,a_l,b,c_l,d_l(2));
L9:nand4 port map(en,a_l,b,c,d_l(3));
L10:nand4 port map(en,a,b_l,c_l,d_l(4));
L11:nand4 port map(en,a,b_l,c,d_l(5));
L12:nand4 port map(en,a,b,c_l,d_l(6));
L13:nand4 port map (en,a,b,c,d_l(7));
end dec;


library ieee; --program for not gate
use ieee.std_logic_1164.all;
entity not1 is
port(a:in std_logic;b:out std_logic);
end not1;
architecture not2 of not1 is
begin
b<=not a;
end not2;

library ieee; ----program for 3 input and gate
use ieee.std_logic_1164.all;
entity and3 is
port(a0,a1,a2:in std_logic;y3:out std_logic);
end and3;
architecture and1 of and3 is
begin
y3<=a0 and a1 and a2;
end and1;

library ieee; ----program for 4 input nand gate
use ieee.std_logic_1164.all;

entity nand4 is
port(a0,a1,a2,a3:in std_logic;y4:out std_logic);
end nand4;
architecture nand3 of nand4 is
signal y4_l:std_logic;
begin
y4_l<=a0 and a1 and a2 and a3;
y4<=not y4_l;
end nand3;