VHDL PROGRAM FOR 4X2 ENCODER IN DATAFLOW STYLE

library ieee;
use ieee.std_logic_1164.all;
entity encod4to2 is
port(d:in std_logic_vector(3 downto 0);
a:out std_logic_vector(1 downto 0));
end encod4to2;
architecture encod4to2 of encod4to2 is
begin
a(0)<=d(1) or d(3);
a(1)<=d(2) or d(3);
end encod4to2;