VHDL PROGRAM FOR 4-bit SHIFT REGISTER IN STRUCTURAL STYLE-IC 74LS94

library ieee;
use ieee.std_logic_1164.all;
entity shiftreg is
port(mode,sin,rsh,lsh:in bit;
qin:in bit_vector(0 to 3);
qout:inout bit_vector(0 to 3));
end shiftreg;
architecture shiftreg_arch of shiftreg is
signal mode_l,clk:bit;
signal sd_l,rd_l:bit:='1';
signal p:bit_vector(0 to 9);
signal t,t_l,qout_l:bit_vector(0 to 3);
component notgate
port(a:in bit; b:out bit);
end component;
component andgate
port(a,b:in bit;c:out bit);
end component;
component norgate
port(a,b:in bit;c:out bit);
end component;
component orgate
port(a,b:in bit; c:out bit);
end component;
component rsff
port(r,s,clk,sd_l,rd_l:in bit;
q,q_l:inout bit);
end component;
begin
L1:notgate port map(mode,mode_l);
L2:andgate port map(sin,mode_l,p(0));
L3:andgate port map(mode,qin(0),p(1));
L4:andgate port map(mode_l,qout(0),p(2));
L5:andgate port map(mode,qin(1),p(3));
L6:andgate port map(mode,qout(1),p(4));
L7:andgate port map(mode,qin(2),p(5));
L8:andgate port map(mode_l,qout(2),p(6));
L9:andgate port map(mode,qin(3),p(7));
L10:andgate port map(mode_l,rsh,p(8));
L11:andgate port map(mode,lsh,p(9));
L12:norgate port map(p(0),p(1),t(0));
L13:norgate port map(p(2),p(3),t(1));
L14:norgate port map(p(4),p(5),t(2));
L15:norgate port map(p(6),p(7),t(3));
L16:orgate port map(p(8),p(9),clk);
L17:notgate port map(t(0),t_l(0));
L18:notgate port map(t(1),t_l(1));
L19:notgate port map(t(2),t_l(2));
L20:notgate port map(t(3),t_l(3));
L21:rsff port map(t(0),t_l(0),clk,sd_l,rd_l,qout(0),qout_l(0));
L22:rsff port map(t(1),t_l(1),clk,sd_l,rd_l,qout(1),qout_l(1));
L23:rsff port map(t(2),t_l(2),clk,sd_l,rd_l,qout(2),qout_l(2));
L24:rsff port map(t(3),t_l(3),clk,sd_l,rd_l,qout(3),qout_l(3));
end shiftreg_arch;