VHDL PROGRAM FOR GENERATING A CLOCK WITH a period of 40ns

hi FRIENDS,
A simple program to generate a clock in VHDL PROGRAMMING.
wait statement is used for delaying.


library ieee;
use ieee.std_logic_1164.all;

entity clkgen is
end clkgen;
architecture clk of clkgen is
constant num_cycles:integer:=10;
signal clk:std_logic:='1';
begin
process
begin
for i in 1 to num_cycles loop
wait for 20 ns;
clk<= not clk;
wait for 20 ns;
end loop;

end process;
end clk;