VHDL PROGRAM FOR 4-bit BINARY ADDER SUBTRACTOR IN STRUCTURAL STYLE

library ieee;
use ieee.std_logic_1164.all;
entity bin4bitaddsub is
port(a,b:in std_logic_vector(3 downto 0);
s:out std_logic_vector(3 downto 0);
cin: in std_logic;
cout:out std_logic);
end bin4bitaddsub;
architecture bin4bitaddsub of bin4bitaddsub is
signal c:std_logic_vector(0 to 2);
signal d:std_logic_vector(3 downto 0);
component xor_2
port(a,b:in std_logic;
c:out std_logic);
end component;
component fulladdD
port(x,y,cin:in std_logic;
s,cout:out std_logic);
end component;
begin
l1:xor_2 port map(b(0),cin,d(0));
l2:xor_2 port map(b(1),cin,d(1));
l3:xor_2 port map(b(2),cin,d(2));
l4:xor_2 port map(b(3),cin,d(3));
l5:fulladdD port map(a(0),d(0),cin,s(0),c(0));
l6:fulladdD port map(a(1),d(1),c(0),s(1),c(1));
l7:fulladdD port map(a(2),d(2),c(1),s(2),c(2));
l8:fulladdD port map(a(3),d(3),c(2),s(3),cout);
end bin4bitaddsub;

library ieee;
use ieee.std_logic_1164.all;
entity xor_2 is
port(a,b:in std_logic;
c:out std_logic);
end xor_2;
architecture xor2 of xor_2 is
begin
c<=a xor b;
end xor2;

library ieee;
use ieee.std_logic_1164.all;
entity fulladdD is
port(x,y,cin:in std_logic;
s,cout:out std_logic);
end fulladdD;
architecture full of fulladdD is
begin
s <= x xor y xor cin;
cout<=(x and y) or (x and cin) or (y and cin);
end full;