VHDL PROGRAM FOR PRIME NUMBERS IN STRUCTURAL STYLE

library ieee;
use ieee.std_logic_1164.all;
entity or4 is
port(i0,i1,i2,i3:in std_logic;o:out std_logic);
end or4;
architecture or2 of or4 is
begin
o<=i0 or i1 or i2 or i3;
end or2;


library ieee;
use ieee.std_logic_1164.all;
entity and2 is
port(i0,i1:in std_logic;o:out std_logic);
end and2;
architecture and2_arch of and2 is
begin
o<=i0 and i1;
end and2_arch;


library ieee;
use ieee.std_logic_1164.all;
entity and3 is
port(i0,i1,i2:in std_logic;o:out std_logic);
end and3;
architecture and3_arch of and3 is
begin
o<=i0 and i1 and i2;
end and3_arch;


library ieee;
use ieee.std_logic_1164.all;
entity inv is
port(i:in std_logic; o:out std_logic);
end inv;
architecture inv_arch of inv is
begin
o<=not i ;
end inv_arch;

library ieee;
use ieee.std_logic_1164.all;
entity prime is
port(n: in std_logic_vector(3 downto 0);
f:out std_logic);
end prime;

architecture prime1_arch of prime is
signal x1,x2,x3,a1,a2,a3,a4 :std_logic;
component INV port(i:in std_logic; o:out std_logic); end component;
component and2 port(i0,i1:in std_logic; o:out std_logic); end component;
component and3 port(i0,i1,i2:in std_logic; o:out std_logic); end component;
component or4 port(i0,i1,i2,i3:in std_logic; o:out std_logic); end component;
begin
U1:INV port map(n(3),x1);
U2:INV port map(n(2),x2);
U3:INV port map(n(1),x3);
U4:AND2 port map(x1,n(0),a1);
U5:AND3 PORT MAP(x1,x2,n(1),a2);
U6:AND3 port map(x2,n(1),n(0),a3);
U7:AND3 port map(n(2),x3,n(0),a4);
U8:or4 port map(a1,a2,a3,a4,f);
end prime1_arch;

1 comments:

Unknown said...

Can u pls post the circuit diagram of this code.
my email is aditirajendran94@gmail.com