VHDL PROGRAM FOR T-FLIPFLOP IN BEHAVIOURAL STYLE

library ieee;
use ieee.std_logic_1164.all;
entity tff1 is
port(t,sd_l,rd_l,clk:in bit; q:inout bit);
end tff1;
architecture tff1_arch of tff1 is
begin
process(clk)
begin

if(sd_l='1' and rd_l='0') then
q<='0';
elsif(sd_l='0' and rd_l='1') then
q<='1';
elsif(sd_l='1' and rd_l='1') then
if(clk'event and clk='0') then
if(t='0') then q<='0';
elsif(t='1') then q<=not q;
end if;
end if;
end if;

end process;


end tff1_arch;