VHDL PROGRAM FOR 4X2 ENCODER IN DATAFLOW STYLE

library ieee;
use ieee.std_logic_1164.all;
entity encod4to2 is
port(d:in std_logic_vector(3 downto 0);
a:out std_logic_vector(1 downto 0));
end encod4to2;
architecture encod4to2 of encod4to2 is
begin
a(0)<=d(1) or d(3);
a(1)<=d(2) or d(3);
end encod4to2;

VHDL PROGRAM FOR 4-bit BINARY ADDER SUBTRACTOR IN STRUCTURAL STYLE

library ieee;
use ieee.std_logic_1164.all;
entity bin4bitaddsub is
port(a,b:in std_logic_vector(3 downto 0);
s:out std_logic_vector(3 downto 0);
cin: in std_logic;
cout:out std_logic);
end bin4bitaddsub;
architecture bin4bitaddsub of bin4bitaddsub is
signal c:std_logic_vector(0 to 2);
signal d:std_logic_vector(3 downto 0);
component xor_2
port(a,b:in std_logic;
c:out std_logic);
end component;
component fulladdD
port(x,y,cin:in std_logic;
s,cout:out std_logic);
end component;
begin
l1:xor_2 port map(b(0),cin,d(0));
l2:xor_2 port map(b(1),cin,d(1));
l3:xor_2 port map(b(2),cin,d(2));
l4:xor_2 port map(b(3),cin,d(3));
l5:fulladdD port map(a(0),d(0),cin,s(0),c(0));
l6:fulladdD port map(a(1),d(1),c(0),s(1),c(1));
l7:fulladdD port map(a(2),d(2),c(1),s(2),c(2));
l8:fulladdD port map(a(3),d(3),c(2),s(3),cout);
end bin4bitaddsub;

library ieee;
use ieee.std_logic_1164.all;
entity xor_2 is
port(a,b:in std_logic;
c:out std_logic);
end xor_2;
architecture xor2 of xor_2 is
begin
c<=a xor b;
end xor2;

library ieee;
use ieee.std_logic_1164.all;
entity fulladdD is
port(x,y,cin:in std_logic;
s,cout:out std_logic);
end fulladdD;
architecture full of fulladdD is
begin
s <= x xor y xor cin;
cout<=(x and y) or (x and cin) or (y and cin);
end full;

VHDL PROGRAM FOR D-flipflop in STRUCTURAL STYLE-IC7474

library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(pre_l,clr_l,d,clk:in std_logic;
q,q_l:inout std_logic);
end dff;
architecture dff_arch of dff is
signal qa,qb,qc,qd:std_logic;
component nand3d
port(a,b,c:in std_logic; y:inout std_logic);
end component;
begin
L1:nand3d port map(pre_l,qd,qb,qa);
L2:nand3d port map(clr_l,qa,clk,qb);
L3:nand3d port map(clk,qb,qd,qc);
L4:nand3d port map(d,clr_l,qc,qd);
L5:nand3d port map(pre_l,qb,q_l,q);
L6:nand3d port map(clr_l,qc,q,q_l);
end dff_arch;

VHDL PROGRAM FOR 4-bit BINARY COUNTER IN STRUCTURAL STYLE-IC 7493

library ieee;
use ieee.std_logic_1164.all;
entity ic7493 is
port(clk,mr1,mr2,sd_l:in bit;
q:inout bit_vector(3 downto 0));
end ic7493;

architecture ic7493_arch of ic7493 is
component notgate
port(a:in bit; b:out bit);
end component;

component nandgate
port(a,b:in bit; c:out bit);
end component;
component jkff
port(j,k,clk,sd_l,rd_l:in bit;
q:inout bit);
end component;
signal j1,k1:bit:='1';
signal mr_l:bit;

begin
L1:nandgate port map(mr1,mr2,mr_l);

L5:jkff port map(j1,k1,clk,sd_l,mr_l,q(0));
L6:jkff port map(j1,k1,q(0),sd_l,mr_l,q(1));
L7:jkff port map(j1,k1,q(1),sd_l,mr_l,q(2));
l8:jkff port map(j1,k1,q(2),sd_l,mr_l,q(3));
end ic7493_arch;

VHDL PROGRAM FOR DECADE COUNTER IN STRUCTURAL STYLE-IC 7490

library ieee;
use ieee.std_logic_1164.all;
entity ic7490 is
port(ms1,ms2,mr1,mr2,clk:in bit;
q:inout bit_vector(3 downto 0));
end ic7490;
architecture ic7490_arch of ic7490 is
component nandgate
port(a,b:in bit; c:out bit);
end component;
component andgate
port(a,b:in bit; c:out bit);
end component;

component jkff
port(j,k,clk,sd_l,rd_l:in bit;
q,q_l:inout bit);
end component;
signal ms,mr,a2:bit;
signal q_l:bit_vector(3 downto 0);
signal j,k:bit:='1';

begin
L1:nandgate port map(ms1,ms2,ms);
L2:nandgate port map(mr1,mr2,mr);
L3:andgate port map(q(1),q(2),a2);
L6:jkff port map(j,k,clk,ms,mr,q(0),q_l(0));
L7:jkff port map(q_l(3),k,q(0),ms,mr,q(1),q_l(1));
L8:jkff port map(j,k,q(1),ms,mr,q(2),q_l(2));
L9:jkff port map(a2,k,q(0),ms,mr,q(3),q_l(3));
end ic7490_arch;

VHDL PROGRAM FOR 4-bit SHIFT REGISTER IN STRUCTURAL STYLE-IC 74LS94

library ieee;
use ieee.std_logic_1164.all;
entity shiftreg is
port(mode,sin,rsh,lsh:in bit;
qin:in bit_vector(0 to 3);
qout:inout bit_vector(0 to 3));
end shiftreg;
architecture shiftreg_arch of shiftreg is
signal mode_l,clk:bit;
signal sd_l,rd_l:bit:='1';
signal p:bit_vector(0 to 9);
signal t,t_l,qout_l:bit_vector(0 to 3);
component notgate
port(a:in bit; b:out bit);
end component;
component andgate
port(a,b:in bit;c:out bit);
end component;
component norgate
port(a,b:in bit;c:out bit);
end component;
component orgate
port(a,b:in bit; c:out bit);
end component;
component rsff
port(r,s,clk,sd_l,rd_l:in bit;
q,q_l:inout bit);
end component;
begin
L1:notgate port map(mode,mode_l);
L2:andgate port map(sin,mode_l,p(0));
L3:andgate port map(mode,qin(0),p(1));
L4:andgate port map(mode_l,qout(0),p(2));
L5:andgate port map(mode,qin(1),p(3));
L6:andgate port map(mode,qout(1),p(4));
L7:andgate port map(mode,qin(2),p(5));
L8:andgate port map(mode_l,qout(2),p(6));
L9:andgate port map(mode,qin(3),p(7));
L10:andgate port map(mode_l,rsh,p(8));
L11:andgate port map(mode,lsh,p(9));
L12:norgate port map(p(0),p(1),t(0));
L13:norgate port map(p(2),p(3),t(1));
L14:norgate port map(p(4),p(5),t(2));
L15:norgate port map(p(6),p(7),t(3));
L16:orgate port map(p(8),p(9),clk);
L17:notgate port map(t(0),t_l(0));
L18:notgate port map(t(1),t_l(1));
L19:notgate port map(t(2),t_l(2));
L20:notgate port map(t(3),t_l(3));
L21:rsff port map(t(0),t_l(0),clk,sd_l,rd_l,qout(0),qout_l(0));
L22:rsff port map(t(1),t_l(1),clk,sd_l,rd_l,qout(1),qout_l(1));
L23:rsff port map(t(2),t_l(2),clk,sd_l,rd_l,qout(2),qout_l(2));
L24:rsff port map(t(3),t_l(3),clk,sd_l,rd_l,qout(3),qout_l(3));
end shiftreg_arch;

VHDL FROGRAM FOR jk-flipflop in BEHAVIOURAL STYLE

library ieee;
use ieee.std_logic_1164.all;
entity jkff is
port(j,k,clk,sd_l,rd_l:in bit;
q,q_l:inout bit);
end jkff;

architecture jkff_arch of jkff is
begin
process(clk)
begin
if(rd_l='0' and sd_l='1')
then q<='0';
elsif(rd_l='1' and sd_l='0')
then q<='1';
elsif(rd_l='1' and sd_l='1')
then if(clk'event and clk='0')
then
if(j='0' and k='1') then q<='0';
elsif(j='1' and k='0') then q<='1';
elsif(j='0' and k='0') then q<=q;
elsif(j='1' and k='1') then q<=not q;
end if;
end if;
end if;
end process;
q_l<=not q;
end jkff_arch;