marvelous view

wideband wireless antenna ieee paper

IEEE paper on wireless antenna.......

http://www.ziddu.com/download/6852600/ieeepaperwidebandwirelessantenna.pdf.html

useful for engineering students in ece stream and for those who are interested in antennas

vlsi advancements

Advancements in VLSI has made it attractive to package multiple processors into a single multichip
or a board module. There is an increasing trend towards using such processor-clusters in
large multiprocessor design. Past research on designing processor-cluster based systems has focused
mainly in studying the packaging technologies affecting the inter-cluster network. To make
processor-cluster based multiprocessor design more attractive, there is a strong need to understand
the details about the topology inside the cluster, its memory organization, and the impact of this
organization on system performance. In this paper we focus on such aspects of processor-cluster
design with an overall objective to support a logically shared address programming model. We analyze
the communication costs for accesing inter-cluster and intra-cluster memories under different
cluster organizations. The merits of these organizations are evaluated based on the performance
of collective communication algorithms, which occur frequently in appplications. In this paper
we focus on implementing the broadcast collective communication algorithm, Umesh, on clustered
systems. Our results indicate that cluster organizations like bus and crossbar which allow memory
inside a cluster to be accessed without messaging overheads, outperform other organizations because
of faster intra-cluster access. We also demonstrate that such faster access can be exploited to
design better algorithms on clustered systems. We propose a new algorithm - clus mesh for broadcasting
on clustered meshes. For reasonably faster communication within clusters, this algorithm
can outperform the existing umesh algorithm by upto 20%.

VHDL PROGRAM FOR GENERATING A CLOCK WITH a period of 40ns

hi FRIENDS,
A simple program to generate a clock in VHDL PROGRAMMING.
wait statement is used for delaying.


library ieee;
use ieee.std_logic_1164.all;

entity clkgen is
end clkgen;
architecture clk of clkgen is
constant num_cycles:integer:=10;
signal clk:std_logic:='1';
begin
process
begin
for i in 1 to num_cycles loop
wait for 20 ns;
clk<= not clk;
wait for 20 ns;
end loop;

end process;
end clk;

VHDL PROGRAM FOR THREE INPUT LOGIC GATES USING CASE STATEMENT IN BEHAVIOURAL STYLE

library IEEE;
use IEEE.std_logic_1164.all;
entity comp is
port (
altbin: in STD_LOGIC;
aeqbin: in STD_LOGIC;
agtbin: in STD_LOGIC;
a: in STD_LOGIC_VECTOR (3 downto 0);
b: in STD_LOGIC_VECTOR (3 downto 0);
agtbout: out STD_LOGIC;
aeqbout: out STD_LOGIC;
altbout: out STD_LOGIC
);
end comp;
architecture comp of comp is
begin
process(a,b,agtbin,aeqbin,altbin)
begin
agtbout<='0'; --initializes the outputs to ‘0’
aeqbout<='0';
altbout<='0';
if aeqbin='1' then
if a=b then aeqbout<='1';
elsif a>b then agtbout<='1';
elsif (a
end if;
elsif (altbin/=agtbin)then
agtbout<=agtbin;
altbout<=altbin;
end if;
end process;
end Comp;

VHDL PROGRAM FOR COMPARATOR IN BEHAVIOURAL STYLE

library IEEE;
use IEEE.std_logic_1164.all;
entity comp is
port (
altbin: in STD_LOGIC;
aeqbin: in STD_LOGIC;
agtbin: in STD_LOGIC;
a: in STD_LOGIC_VECTOR (3 downto 0);
b: in STD_LOGIC_VECTOR (3 downto 0);
agtbout: out STD_LOGIC;
aeqbout: out STD_LOGIC;
altbout: out STD_LOGIC
);
end comp;
architecture comp of comp is
begin
process(a,b,agtbin,aeqbin,altbin)
begin
agtbout<='0'; --initializes the outputs to ‘0’
aeqbout<='0';
altbout<='0';
if aeqbin='1' then
if a=b then aeqbout<='1';
elsif a>b then agtbout<='1';
elsif (a
end if;
elsif (altbin/=agtbin)then
agtbout<=agtbin;
altbout<=altbin;
end if;
end process;
end Comp;

VHDL PROGRAM FOR SERIAL IN SERIAL OUT SHIFT REGISTER IN BEHAVIOURAL STYLE

library ieee;
use ieee.std_logic_1164.all;
entity shiftsi is
port(C, SI : in std_logic;
SO : out std_logic);
end shiftsi;
architecture archi of shiftsi is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
tmp(0) <= SI;
if (C'event and C='1') then
for i in 0 to 6 loop
tmp(i+1) <= tmp(i);
end loop;

end if;
end process;
SO <= tmp(7);
end archi;